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Hello,
the issue occurs with every kernel I tested so far 4.14 - 4-17 but in 4.14 and 4.15 I have a workaround: kernelparamer i915.enable_rc6=0
My issue:
At first this error occurs
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrunAfter that the screen flickers on all tty2 ... tty6 and on tty7 (graphic) on highest resolution (2560x1440).
Disabling rc6 worked, but since 4.16 the kernel parameter got removed.
What Ive tried so far:
i915.enable_psr=0
i915.edv_pswing=0
and modifying the kernel and building it afterwards...
Possible solutions (what I think)
- a real fix maybe?
- maybe someone can help me out what Im missing with patching /drivers/gpu/drm/i915/intel_pm.c
Thats my patch for the 4.17 kernel:
.../drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++-------------
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8da4dc..4b6c28d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6519,16 +6519,16 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
enable_rc6 = false;
}
-
- return enable_rc6;
+ return false;
+ //return enable_rc6;
}
static bool sanitize_rc6(struct drm_i915_private *i915)
{
struct intel_device_info *info = mkwrite_device_info(i915);
- /* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(i915))
+ /* Powersaving is controlled by the host when inside a VM */
+ if (intel_vgpu_active(i915))
info->has_rc6 = 0;
if (info->has_rc6 &&
@@ -6536,16 +6536,16 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
DRM_INFO("RC6 disabled by BIOS\n");
info->has_rc6 = 0;
}
-
+ info->has_rc6 = 0;
/*
* We assume that we do not have any deep rc6 levels if we don't have
* have the previous rc6 level supported, i.e. we use HAS_RC6()
* as the initial coarse check for rc6 in general, moving on to
* progressively finer/deeper levels.
*/
- if (!info->has_rc6 && info->has_rc6p)
+ if (!info->has_rc6 && info->has_rc6p)
info->has_rc6p = 0;
-
+
return info->has_rc6;
}
@@ -6717,12 +6717,11 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
* WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
*/
- if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
+ if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
I915_WRITE(GEN9_PG_ENABLE, 0);
else
- I915_WRITE(GEN9_PG_ENABLE,
+ I915_WRITE(GEN9_PG_ENABLE,
GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
-
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -6751,12 +6750,10 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
/* 3: Enable RC6 */
-
I915_WRITE(GEN6_RC_CONTROL,
GEN6_RC_CTL_HW_ENABLE |
GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_RC6_ENABLE);
-
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -6840,7 +6837,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
- /* We don't use those on Haswell */
+ /* We don't use those on Haswell */
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
if (HAS_RC6p(dev_priv))
rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
@@ -6850,7 +6847,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
rc6_mask |
GEN6_RC_CTL_EI_MODE(1) |
GEN6_RC_CTL_HW_ENABLE);
-
+
rc6vids = 0;
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
if (IS_GEN6(dev_priv) && ret) {
@@ -7332,10 +7329,9 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
pcbr = I915_READ(VLV_PCBR);
/* 3: Enable RC6 */
- rc6_mode = 0;
if (pcbr >> VLV_PCBR_ADDR_SHIFT)
rc6_mode = GEN7_RC_CTL_TO_MODE;
- I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
@@ -7418,11 +7414,9 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
VLV_RENDER_RC0_COUNT_EN |
VLV_MEDIA_RC6_COUNT_EN |
VLV_RENDER_RC6_COUNT_EN));
-
I915_WRITE(GEN6_RC_CONTROL,
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
-
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -8116,15 +8110,13 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
return;
if (IS_CHERRYVIEW(dev_priv))
- cherryview_enable_rc6(dev_priv);
+ cherryview_disable_rc6(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
- valleyview_enable_rc6(dev_priv);
+ valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 9)
- gen9_enable_rc6(dev_priv);
- else if (IS_BROADWELL(dev_priv))
- gen8_enable_rc6(dev_priv);
+ gen9_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
- gen6_enable_rc6(dev_priv);
+ gen6_disable_rc6(dev_priv);
dev_priv->gt_pm.rc6.enabled = true;
}EDIT:
I found a solution:
Setting this kernel parameter
intel_idle.max_cstate=1as mentioned here https://bugzilla.redhat.com/show_bug.cgi?id=1573482
solved the screen flickering
Last edited by Bl4d3s (2018-07-12 19:53:34)
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