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#1 2019-02-26 12:58:55

Akusari
Member
Registered: 2019-02-26
Posts: 18

[solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

Hello!

I just wanna know what up, or better, the current standing of kernel support, specially fan and volt view, for B450 and X470 mainboards (chipsets) whih can be used for LM-Sensors or any other software? So far as i understood, there is no support, because AMD is hidding technical specs which are needed to write drivers  ?! :-(

Thanks you!

Regards
Daniel

Last edited by Akusari (2019-03-02 20:27:19)

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#2 2019-02-26 16:51:26

Slithery
Administrator
From: Norfolk, UK
Registered: 2013-12-01
Posts: 5,776

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

No problems here on my 2700X.


No, it didn't "fix" anything. It just shifted the brokeness one space to the right. - jasonwryan
Closing -- for deletion; Banning -- for muppetry. - jasonwryan

aur - dotfiles

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#3 2019-02-26 19:12:48

Gusar
Member
Registered: 2009-08-25
Posts: 3,605

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

CPU temperature readout is supported, but only for the whole package, not per-core temperatures. And that's indeed because AMD doesn't provide the info. There are two versions of the relevant document, the one that has all the info is available only under an NDA: https://github.com/lm-sensors/lm-sensor … -299743322. To that I can only say "WTF, AMD???"

Sensor readout other than CPU temp is up to the board, specifically the Super-I/O chip that's on there. This chip is not provided by AMD, the most common ones nowadays are ITE and Nuvoton. They are not very eager to share info, but this has been the case since forever, it didn't start with Ryzen and is not limited to AMD boards. So volt reporting can be hit-or-miss, but fan control usually works.

There's a problem though, which is that the it87 driver (which handles ITE chips) has gone unmaintained. The in-kernel version of it87 is old, it doesn't support the chip on my board. The out-of-kernel version is newer, it supports my chip, but without further maintenance it's possible that won't be the case anymore with a future board.

From what I've seen Asrock and MSI tend to go with Nuvoton, Asus and Gigabyte go with ITE. But don't take that as a hard rule.

Last edited by Gusar (2019-02-26 19:30:25)

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#4 2019-02-26 21:14:30

Akusari
Member
Registered: 2019-02-26
Posts: 18

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

Thank you very much! You save my day and i was able to look much deeper in the whole story in my hardware case (NCT6796D). I'll try to create own patches for  I/O mapping of similar chip versions. Thx :-) (Probably there are some patches available and i only need to do a backport for 4.19-lts)

Regards
Daniel

@Post info: https://git.kernel.org/pub/scm/linux/ke … h=v5.0-rc8 (Backport possible :-)

Last edited by Akusari (2019-02-26 21:25:59)

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#5 2019-02-27 00:04:35

loqs
Member
Registered: 2014-03-06
Posts: 17,192

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

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#6 2019-02-27 14:13:40

Akusari
Member
Registered: 2019-02-26
Posts: 18

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

I'm sorry there was a little typo from my side. :-(

My chip is named nct6797(D/E) with the id 0xd451.
Further more i have to take a look whats up with the variants of 0xd450 and 0xd451. If they are really register/bit compatible the work can go on. :-)

I'll keep you up to date.

Regards
Daniel

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#7 2019-03-02 20:24:15

Akusari
Member
Registered: 2019-02-26
Posts: 18

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

Hello guys!

Okay, here is the patch for the ARCH LTS kernel to support NCT 6997 i/o chip for hardware monitor. :-)

You can download my pkgbuild file and additional files from my dropbox: https://www.dropbox.com/s/qw9ljgmh5p4mk … ar.gz?dl=0
simply do a makepkg -s

patches:

PKGBUILD:

diff -Pu linux-lts/repos/core-x86_64/PKGBUILD linux-lts-4.19.x/repos/core-x86_64/PKGBUILD
--- linux-lts/repos/core-x86_64/PKGBUILD    2019-03-02 20:54:37.024817589 +0100
+++ linux-lts-4.19.x/repos/core-x86_64/PKGBUILD    2019-03-02 21:00:16.712518790 +0100
@@ -1,7 +1,8 @@
# Maintainer: Andreas Radke <andyrtr@archlinux.org>
+# Add nct 6997 patchfile by Daniel Mehrmann <daniel.mehrmann@gmx.de>

-pkgbase=linux-lts
-#pkgbase=linux-lts-custom
+#pkgbase=linux-lts
+pkgbase=linux-lts-dm
_srcname=linux-4.19
pkgver=4.19.26
pkgrel=1
@@ -16,7 +17,8 @@
         '60-linux.hook'  # pacman hook for depmod
         '90-linux.hook'  # pacman hook for initramfs regeneration
         'linux-lts.preset'   # standard config files for mkinitcpio ramdisk
-        0001-add-sysctl-to-disallow-unprivileged-CLONE_NEWUSER-by.patch)
+        0001-add-sysctl-to-disallow-unprivileged-CLONE_NEWUSER-by.patch
+        0999-add-nct-6997-support.patch)
validpgpkeys=('ABAF11C65A2970B130ABE3C479BE3E4300411886' # Linus Torvalds <torvalds@linux-foundation.org>
               '647F28654894E3BD457199BE38DBBDC86092693E' # Greg Kroah-Hartman (Linux kernel stable release signing key) <greg@kroah.com>
              )
@@ -28,7 +30,8 @@
             'ae2e95db94ef7176207c690224169594d49445e04249d2499e9d2fbc117a0b21'
             '75f99f5239e03238f88d1a834c50043ec32b1dc568f2cc291b07d04718483919'
             'ad6344badc91ad0630caacde83f7f9b97276f80d26a20619a87952be65492c65'
-            '36b1118c8dedadc4851150ddd4eb07b1c58ac5bbf3022cc2501a27c2b476da98')
+            '36b1118c8dedadc4851150ddd4eb07b1c58ac5bbf3022cc2501a27c2b476da98'
+            'faf2c98c347ecc8e54c2d5e09504ac6dc1e907ac34cd5336faa5a1eb189003d1')

_kernelname=${pkgbase#linux}

@@ -47,6 +50,9 @@
   # disable USER_NS for non-root users by default
   patch -Np1 -i ../0001-add-sysctl-to-disallow-unprivileged-CLONE_NEWUSER-by.patch

+  # patch for nct 6997 i/o chip support (backport)
+  patch -Np1 -i ../0999-add-nct-6997-support.patch
+
   cp -Tf ../config .config

   if [ "${_kernelname}" != "" ]; then

patchfile: 0999-add-nct-6997-support.patch

diff -Pur linux-lts/repos/core-x86_64/0999-add-nct-6997-support.patch linux-lts-4.19.x/repos/core-x86_64/0999-add-nct-6997-support.patch
--- linux-lts/repos/core-x86_64/0999-add-nct-6997-support.patch    1970-01-01 01:00:00.000000000 +0100
+++ linux-lts-4.19.x/repos/core-x86_64/0999-add-nct-6997-support.patch    2019-02-27 14:58:43.164617144 +0100
@@ -0,0 +1,509 @@
+--- linux-4.19/drivers/hwmon/nct6775.c    2018-10-22 08:37:37.000000000 +0200
++++ ../nct6775-50.c    2019-02-27 14:02:15.542804502 +0100
+@@ -42,6 +42,10 @@
+  * nct6793d    15      6       6       2+6    0xd120 0xc1    0x5ca3
+  * nct6795d    14      6       6       2+6    0xd350 0xc1    0x5ca3
+  * nct6796d    14      7       7       2+6    0xd420 0xc1    0x5ca3
++ * nct6797d    14      7       7       2+6    0xd450 0xc1    0x5ca3
++ *                                           (0xd451)
++ * nct6798d    14      7       7       2+6    0xd428 0xc1    0x5ca3
++ *                                           (0xd429)
+  *
+  * #temp lists the number of monitored temperature sources (first value) plus
+  * the number of directly connectable temperature sensors (second value).
+@@ -69,7 +73,7 @@
+ #define USE_ALTERNATE
+
+ enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
+-         nct6795, nct6796 };
++         nct6795, nct6796, nct6797, nct6798 };
+
+ /* used to set data->name = nct6775_device_names[data->sio_kind] */
+ static const char * const nct6775_device_names[] = {
+@@ -82,6 +86,8 @@
+     "nct6793",
+     "nct6795",
+     "nct6796",
++    "nct6797",
++    "nct6798",
+ };
+
+ static const char * const nct6775_sio_names[] __initconst = {
+@@ -94,6 +100,8 @@
+     "NCT6793D",
+     "NCT6795D",
+     "NCT6796D",
++    "NCT6797D",
++    "NCT6798D",
+ };
+
+ static unsigned short force_id;
+@@ -129,7 +137,9 @@
+ #define SIO_NCT6793_ID        0xd120
+ #define SIO_NCT6795_ID        0xd350
+ #define SIO_NCT6796_ID        0xd420
+-#define SIO_ID_MASK        0xFFF0
++#define SIO_NCT6797_ID        0xd450
++#define SIO_NCT6798_ID        0xd428
++#define SIO_ID_MASK        0xFFF8
+
+ enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
+
+@@ -504,7 +514,7 @@
+ static const u16 NCT6779_REG_FAN[] = {
+     0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
+ static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
+-    0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
++    0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0x64f };
+
+ static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
+     0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
+@@ -704,10 +714,10 @@
+     "PCH_CHIP_TEMP",
+     "PCH_CPU_TEMP",
+     "PCH_MCH_TEMP",
+-    "PCH_DIM0_TEMP",
+-    "PCH_DIM1_TEMP",
+-    "PCH_DIM2_TEMP",
+-    "PCH_DIM3_TEMP",
++    "Agent0 Dimm0",
++    "Agent0 Dimm1",
++    "Agent1 Dimm0",
++    "Agent1 Dimm1",
+     "BYTE_TEMP0",
+     "BYTE_TEMP1",
+     "PECI Agent 0 Calibration",
+@@ -742,10 +752,10 @@
+     "PCH_CHIP_TEMP",
+     "PCH_CPU_TEMP",
+     "PCH_MCH_TEMP",
+-    "PCH_DIM0_TEMP",
+-    "PCH_DIM1_TEMP",
+-    "PCH_DIM2_TEMP",
+-    "PCH_DIM3_TEMP",
++    "Agent0 Dimm0",
++    "Agent0 Dimm1",
++    "Agent1 Dimm0",
++    "Agent1 Dimm1",
+     "BYTE_TEMP0",
+     "BYTE_TEMP1",
+     "PECI Agent 0 Calibration",
+@@ -757,6 +767,44 @@
+ #define NCT6796_TEMP_MASK    0xbfff0ffe
+ #define NCT6796_VIRT_TEMP_MASK    0x80000c00
+
++static const char *const nct6798_temp_label[] = {
++    "",
++    "SYSTIN",
++    "CPUTIN",
++    "AUXTIN0",
++    "AUXTIN1",
++    "AUXTIN2",
++    "AUXTIN3",
++    "AUXTIN4",
++    "SMBUSMASTER 0",
++    "SMBUSMASTER 1",
++    "Virtual_TEMP",
++    "Virtual_TEMP",
++    "",
++    "",
++    "",
++    "",
++    "PECI Agent 0",
++    "PECI Agent 1",
++    "PCH_CHIP_CPU_MAX_TEMP",
++    "PCH_CHIP_TEMP",
++    "PCH_CPU_TEMP",
++    "PCH_MCH_TEMP",
++    "Agent0 Dimm0",
++    "Agent0 Dimm1",
++    "Agent1 Dimm0",
++    "Agent1 Dimm1",
++    "BYTE_TEMP0",
++    "BYTE_TEMP1",
++    "",
++    "",
++    "",
++    "Virtual_TEMP"
++};
++
++#define NCT6798_TEMP_MASK    0x8fff0ffe
++#define NCT6798_VIRT_TEMP_MASK    0x80000c00
++
+ /* NCT6102D/NCT6106D specific data */
+
+ #define NCT6106_REG_VBAT    0x318
+@@ -1288,6 +1336,8 @@
+     case nct6793:
+     case nct6795:
+     case nct6796:
++    case nct6797:
++    case nct6798:
+         return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
+           (reg & 0xfff0) == 0x4c0 ||
+           reg == 0x402 ||
+@@ -1643,6 +1693,8 @@
+         case nct6793:
+         case nct6795:
+         case nct6796:
++        case nct6797:
++        case nct6798:
+             reg = nct6775_read_value(data,
+                     data->REG_CRITICAL_PWM_ENABLE [fucking forum code doesn't allow array counters]);
+             if (reg & data->CRITICAL_PWM_ENABLE_MASK)
+@@ -2847,6 +2899,8 @@
+  * Fan speed tolerance is a tricky beast, since the associated register is
+  * a tick counter, but the value is reported and configured as rpm.
+  * Compute resulting low and high rpm values and report the difference.
++ * A fan speed tolerance only makes sense if a fan target speed has been
++ * configured, so only display values other than 0 if that is the case.
+  */
+ static ssize_t
+ show_speed_tolerance(struct device *dev, struct device_attribute *attr,
+@@ -2855,19 +2909,23 @@
+     struct nct6775_data *data = nct6775_update_device(dev);
+     struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
+     int nr = sattr->index;
+-    int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
+-    int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
+-    int tolerance;
++    int target = data->target_speed[nr];
++    int tolerance = 0;
+
+-    if (low <= 0)
+-        low = 1;
+-    if (high > 0xffff)
+-        high = 0xffff;
+-    if (high < low)
+-        high = low;
++    if (target) {
++        int low = target - data->target_speed_tolerance[nr];
++        int high = target + data->target_speed_tolerance[nr];
++
++        if (low <= 0)
++            low = 1;
++        if (high > 0xffff)
++            high = 0xffff;
++        if (high < low)
++            high = low;
+
+-    tolerance = (fan_from_reg16(low, data->fan_div[nr])
+-             - fan_from_reg16(high, data->fan_div[nr])) / 2;
++        tolerance = (fan_from_reg16(low, data->fan_div[nr])
++                 - fan_from_reg16(high, data->fan_div[nr])) / 2;
++    }
+
+     return sprintf(buf, "%d\n", tolerance);
+ }
+@@ -3071,6 +3129,8 @@
+         case nct6793:
+         case nct6795:
+         case nct6796:
++        case nct6797:
++        case nct6798:
+             nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
+                         val);
+             reg = nct6775_read_value(data,
+@@ -3430,7 +3490,6 @@
+     bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
+     bool pwm6pin = false, pwm7pin = false;
+     int sioreg = data->sioreg;
+-    int regval;
+
+     /* Store SIO_REG_ENABLE for use during resume */
+     superio_select(sioreg, NCT6775_LD_HWM);
+@@ -3438,10 +3497,10 @@
+
+     /* fan4 and fan5 share some pins with the GPIO and serial flash */
+     if (data->kind == nct6775) {
+-        regval = superio_inb(sioreg, 0x2c);
++        int cr2c = superio_inb(sioreg, 0x2c);
+
+-        fan3pin = regval & BIT(6);
+-        pwm3pin = regval & BIT(7);
++        fan3pin = cr2c & BIT(6);
++        pwm3pin = cr2c & BIT(7);
+
+         /* On NCT6775, fan4 shares pins with the fdc interface */
+         fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
+@@ -3486,85 +3545,131 @@
+         fan4min = fan4pin;
+         pwm3pin = fan3pin;
+     } else if (data->kind == nct6106) {
+-        regval = superio_inb(sioreg, 0x24);
+-        fan3pin = !(regval & 0x80);
+-        pwm3pin = regval & 0x08;
+-    } else {
+-        /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
+-        int regval_1b, regval_2a, regval_2f;
+-        bool dsw_en;
+-
+-        regval = superio_inb(sioreg, 0x1c);
+-
+-        fan3pin = !(regval & BIT(5));
+-        fan4pin = !(regval & BIT(6));
+-        fan5pin = !(regval & BIT(7));
++        int cr24 = superio_inb(sioreg, 0x24);
+
+-        pwm3pin = !(regval & BIT(0));
+-        pwm4pin = !(regval & BIT(1));
+-        pwm5pin = !(regval & BIT(2));
++        fan3pin = !(cr24 & 0x80);
++        pwm3pin = cr24 & 0x08;
++    } else {
++        /*
++         * NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D,
++         * NCT6797D, NCT6798D
++         */
++        int cr1a = superio_inb(sioreg, 0x1a);
++        int cr1b = superio_inb(sioreg, 0x1b);
++        int cr1c = superio_inb(sioreg, 0x1c);
++        int cr1d = superio_inb(sioreg, 0x1d);
++        int cr2a = superio_inb(sioreg, 0x2a);
++        int cr2b = superio_inb(sioreg, 0x2b);
++        int cr2d = superio_inb(sioreg, 0x2d);
++        int cr2f = superio_inb(sioreg, 0x2f);
++        bool dsw_en = cr2f & BIT(3);
++        bool ddr4_en = cr2f & BIT(4);
++        int cre0;
++        int creb;
++        int cred;
++
++        superio_select(sioreg, NCT6775_LD_12);
++        cre0 = superio_inb(sioreg, 0xe0);
++        creb = superio_inb(sioreg, 0xeb);
++        cred = superio_inb(sioreg, 0xed);
++
++        fan3pin = !(cr1c & BIT(5));
++        fan4pin = !(cr1c & BIT(6));
++        fan5pin = !(cr1c & BIT(7));
++
++        pwm3pin = !(cr1c & BIT(0));
++        pwm4pin = !(cr1c & BIT(1));
++        pwm5pin = !(cr1c & BIT(2));
+
+-        regval = superio_inb(sioreg, 0x2d);
+         switch (data->kind) {
+         case nct6791:
++            fan6pin = cr2d & BIT(1);
++            pwm6pin = cr2d & BIT(0);
++            break;
+         case nct6792:
+-            fan6pin = regval & BIT(1);
+-            pwm6pin = regval & BIT(0);
++            fan6pin = !dsw_en && (cr2d & BIT(1));
++            pwm6pin = !dsw_en && (cr2d & BIT(0));
+             break;
+         case nct6793:
++            fan5pin |= cr1b & BIT(5);
++            fan5pin |= creb & BIT(5);
++
++            fan6pin = !dsw_en && (cr2d & BIT(1));
++            fan6pin |= creb & BIT(3);
++
++            pwm5pin |= cr2d & BIT(7);
++            pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
++
++            pwm6pin = !dsw_en && (cr2d & BIT(0));
++            pwm6pin |= creb & BIT(2);
++            break;
+         case nct6795:
++            fan5pin |= cr1b & BIT(5);
++            fan5pin |= creb & BIT(5);
++
++            fan6pin = (cr2a & BIT(4)) &&
++                    (!dsw_en || (cred & BIT(4)));
++            fan6pin |= creb & BIT(3);
++
++            pwm5pin |= cr2d & BIT(7);
++            pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
++
++            pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
++            pwm6pin |= creb & BIT(2);
++            break;
+         case nct6796:
+-            regval_1b = superio_inb(sioreg, 0x1b);
+-            regval_2a = superio_inb(sioreg, 0x2a);
+-            regval_2f = superio_inb(sioreg, 0x2f);
+-            dsw_en = regval_2f & BIT(3);
+-
+-            if (!pwm5pin)
+-                pwm5pin = regval & BIT(7);
+-
+-            if (!fan5pin)
+-                fan5pin = regval_1b & BIT(5);
+-
+-            superio_select(sioreg, NCT6775_LD_12);
+-            if (data->kind != nct6796) {
+-                int regval_eb = superio_inb(sioreg, 0xeb);
+-
+-                if (!dsw_en) {
+-                    fan6pin = regval & BIT(1);
+-                    pwm6pin = regval & BIT(0);
+-                }
++            fan5pin |= cr1b & BIT(5);
++            fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0));
++            fan5pin |= creb & BIT(5);
+
+-                if (!fan5pin)
+-                    fan5pin = regval_eb & BIT(5);
+-                if (!pwm5pin)
+-                    pwm5pin = (regval_eb & BIT(4)) &&
+-                        !(regval_2a & BIT(0));
+-                if (!fan6pin)
+-                    fan6pin = regval_eb & BIT(3);
+-                if (!pwm6pin)
+-                    pwm6pin = regval_eb & BIT(2);
+-            }
++            fan6pin = (cr2a & BIT(4)) &&
++                    (!dsw_en || (cred & BIT(4)));
++            fan6pin |= creb & BIT(3);
+
+-            if (data->kind == nct6795 || data->kind == nct6796) {
+-                int regval_ed = superio_inb(sioreg, 0xed);
++            fan7pin = !(cr2b & BIT(2));
+
+-                if (!fan6pin)
+-                    fan6pin = (regval_2a & BIT(4)) &&
+-                      (!dsw_en ||
+-                       (dsw_en && (regval_ed & BIT(4))));
+-                if (!pwm6pin)
+-                    pwm6pin = (regval_2a & BIT(3)) &&
+-                      (regval_ed & BIT(2));
+-            }
++            pwm5pin |= cr2d & BIT(7);
++            pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0));
++            pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
+
+-            if (data->kind == nct6796) {
+-                int regval_1d = superio_inb(sioreg, 0x1d);
+-                int regval_2b = superio_inb(sioreg, 0x2b);
++            pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
++            pwm6pin |= creb & BIT(2);
+
+-                fan7pin = !(regval_2b & BIT(2));
+-                pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
+-            }
++            pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
++            break;
++        case nct6797:
++            fan5pin |= !ddr4_en && (cr1b & BIT(5));
++            fan5pin |= creb & BIT(5);
++
++            fan6pin = cr2a & BIT(4);
++            fan6pin |= creb & BIT(3);
++
++            fan7pin = cr1a & BIT(1);
++
++            pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
++            pwm5pin |= !ddr4_en && (cr2d & BIT(7));
+
++            pwm6pin = creb & BIT(2);
++            pwm6pin |= cred & BIT(2);
++
++            pwm7pin = cr1d & BIT(4);
++            break;
++        case nct6798:
++            fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3));
++            fan6pin |= cr2a & BIT(4);
++            fan6pin |= creb & BIT(5);
++
++            fan7pin = cr1b & BIT(5);
++            fan7pin |= !(cr2b & BIT(2));
++            fan7pin |= creb & BIT(3);
++
++            pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4));
++            pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3));
++            pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
++
++            pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
++            pwm7pin |= cr2d & BIT(7);
++            pwm7pin |= creb & BIT(2);
+             break;
+         default:    /* NCT6779D */
+             break;
+@@ -3943,8 +4048,12 @@
+     case nct6793:
+     case nct6795:
+     case nct6796:
++    case nct6797:
++    case nct6798:
+         data->in_num = 15;
+-        data->pwm_num = (data->kind == nct6796) ? 7 : 6;
++        data->pwm_num = (data->kind == nct6796 ||
++                 data->kind == nct6797 ||
++                 data->kind == nct6798) ? 7 : 6;
+         data->auto_pwm_num = 4;
+         data->has_fan_div = false;
+         data->temp_fixed_num = 6;
+@@ -3978,6 +4087,7 @@
+             data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
+             break;
+         case nct6795:
++        case nct6797:
+             data->temp_label = nct6795_temp_label;
+             data->temp_mask = NCT6795_TEMP_MASK;
+             data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
+@@ -3987,6 +4097,11 @@
+             data->temp_mask = NCT6796_TEMP_MASK;
+             data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
+             break;
++        case nct6798:
++            data->temp_label = nct6798_temp_label;
++            data->temp_mask = NCT6798_TEMP_MASK;
++            data->virt_temp_mask = NCT6798_VIRT_TEMP_MASK;
++            break;
+         }
+
+         data->REG_CONFIG = NCT6775_REG_CONFIG;
+@@ -4256,6 +4371,8 @@
+     case nct6793:
+     case nct6795:
+     case nct6796:
++    case nct6797:
++    case nct6798:
+         break;
+     }
+
+@@ -4291,6 +4408,8 @@
+         case nct6793:
+         case nct6795:
+         case nct6796:
++        case nct6797:
++        case nct6798:
+             tmp |= 0x7e;
+             break;
+         }
+@@ -4390,7 +4509,8 @@
+
+     if (data->kind == nct6791 || data->kind == nct6792 ||
+         data->kind == nct6793 || data->kind == nct6795 ||
+-        data->kind == nct6796)
++        data->kind == nct6796 || data->kind == nct6797 ||
++        data->kind == nct6798)
+         nct6791_enable_io_mapping(sioreg);
+
+     superio_exit(sioreg);
+@@ -4493,6 +4613,12 @@
+     case SIO_NCT6796_ID:
+         sio_data->kind = nct6796;
+         break;
++    case SIO_NCT6797_ID:
++        sio_data->kind = nct6797;
++        break;
++    case SIO_NCT6798_ID:
++        sio_data->kind = nct6798;
++        break;
+     default:
+         if (val != 0xffff)
+             pr_debug("unsupported chip ID: 0x%04x\n", val);
+@@ -4520,7 +4646,8 @@
+
+     if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
+         sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
+-        sio_data->kind == nct6796)
++        sio_data->kind == nct6796 || sio_data->kind == nct6797 ||
++        sio_data->kind == nct6798)
+         nct6791_enable_io_mapping(sioaddr);
+
+     superio_exit(sioaddr);


Output from sensors:

[daniel@Homer]/$ sensors
nct6797-isa-0a20
Adapter: ISA adapter
in0:                    +0.46 V  (min =  +0.00 V, max =  +1.74 V)
in1:                    +1.01 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in2:                    +3.33 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in3:                    +3.38 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in4:                    +1.01 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in5:                    +0.14 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in6:                    +0.85 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in7:                    +3.33 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in8:                    +3.23 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in9:                    +1.82 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in10:                   +0.00 V  (min =  +0.00 V, max =  +0.00 V)
in11:                   +0.70 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in12:                   +1.15 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in13:                   +0.68 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
in14:                   +1.54 V  (min =  +0.00 V, max =  +0.00 V)  ALARM
fan1:                     0 RPM  (min =    0 RPM)
fan2:                   479 RPM  (min =    0 RPM)
fan3:                   592 RPM  (min =    0 RPM)
fan4:                     0 RPM  (min =    0 RPM)
fan5:                   619 RPM  (min =    0 RPM)
fan6:                   613 RPM  (min =    0 RPM)
SYSTIN:                 +28.0°C  (high = +80.0°C, hyst = +75.0°C)  sensor = CPU diode
CPUTIN:                 +28.0°C  (high = +115.0°C, hyst = +90.0°C)  sensor = thermistor
AUXTIN0:                +34.5°C  (high = +115.0°C, hyst = +90.0°C)  sensor = thermistor
AUXTIN1:               -128.0°C    sensor = thermistor
AUXTIN2:                +43.0°C    sensor = thermistor
AUXTIN3:                 -2.0°C    sensor = thermistor
SMBUSMASTER 0:          +27.5°C 
PCH_CHIP_CPU_MAX_TEMP:   +0.0°C 
PCH_CHIP_TEMP:           +0.0°C 
PCH_CPU_TEMP:            +0.0°C 
intrusion0:            ALARM
intrusion1:            ALARM
beep_enable:           disabled

k10temp-pci-00c3
Adapter: PCI adapter
Tdie:         +27.8°C  (high = +70.0°C)
Tctl:         +27.8°C 

Rergards
Daniel

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#8 2019-03-02 21:02:06

graysky
Wiki Maintainer
From: :wq
Registered: 2008-12-01
Posts: 10,595
Website

Re: [solved][patch added] Support of 2nd Ryzen and chipset (lm-sensors)

@Akusari - Please don't post the entire patch, link it instead or at the minimum use code tags.


CPU-optimized Linux-ck packages @ Repo-ck  • AUR packagesZsh and other configs

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