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johnny.honu

Member

Registered: 2021-04-18

Posts: 18

Chipset PCIe bottleneck question

I have a MSI B560 MAG Torpedo mobo.  The specs say its chipset supports:

• two PCIe slots (one at up to PCIe 3.0 x4 and one at PCIe 3.0 x1);

• two M.2 slots (each at up to PCIe 3.0 x4); and

• six SATA ports.

My CPU is an Intel i3-10320.  The specs say it supports:

• up to 16 PCIe lanes

• (plus, I think it also has 4 PCIe lanes that serve the chipset, but Intel doesn't "advertise" that in their specs).

Are the 16 PCIe lanes on the CPU reserved for expansion slots that don't run through the chipset, or can the chipset direct traffic from its PCIe slots and M.2 slots to any of the 16 PCIe lanes on the CPU?

Are the SATA ports also served by those four "unadvertised" PCIe slots, or do they have some other connection, like DMI (based on most of what I've read, I think it is DMI, but am not sure)?

loqs

Member

Registered: 2014-03-06

Posts: 18,917

Re: Chipset PCIe bottleneck question

Did you try a web search for B560 chipset diagram?
https://www.funkykit.com/wp-content/upl … iagram.jpg
https://cdn.videocardz.com/1/2020/03/In … oCardz.jpg

johnny.honu

Member

Registered: 2021-04-18

Posts: 18

Re: Chipset PCIe bottleneck question

Thanks for the diagrams.  I think my question was worded awkwardly, and I don't think the diagrams quite address it.  My CPU (i3 10th gen) only has 16 advertised pcie lanes.  How are those 16 pcie lanes shared between the direct-to-cpu pcie slots on the motherboard and the chipset pcie slots?  In my case, my motherboard has more pcie lanes than my CPU can handle.  I'm hoping to understand how the lanes are assigned so I can make decisions on what slots (direct-to-cpu or thru chipset) to use for what hardware.

Slithery

Administrator

From: Norfolk, UK

Registered: 2013-12-01

Posts: 5,776

Re: Chipset PCIe bottleneck question

It's pretty clear from your motherboard manual that the 16 PCIe lanes are only available for the primary slot. All other communication (expect the primary M2 slot) is shared and goes through the chipset DMI lanes.

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loqs

Member

Registered: 2014-03-06

Posts: 18,917

Re: Chipset PCIe bottleneck question

https://download.msi.com/archive/mnu_ex … 1_v2.1.pdf page 24 block diagram as Slithery wrote shows how all the lanes are assigned and routed.
Edit:
https://ark.intel.com/content/www/us/en … ipset.html -> documentation -> 635218 ( Intel®500 Series Chipset FamilyPlatform Controller HubDatasheet, Volume 1 of 2 )
Shows 4 DMI lanes for the B560 while the motherboard manual shows 8.

Last edited by loqs (2021-05-17 23:25:29)

johnny.honu

Member

Registered: 2021-04-18

Posts: 18

Re: Chipset PCIe bottleneck question

Ahhh... yes.  Thank you Slithery and loqs, it has been right under my nose and I have been googling and searching all the wrong sources (my apologies for you having to point out the obvious to me).   I somehow mistakenly acquired the belief that some of the 16 PCIe lanes on my CPU could be shared with the chipset, which is not the case.  The diagram in the MSI manual labeled it as only going through DMI, and I think the Intel manual must be correct that it is only DMI x4 (I'm guessing MSI has a typo).  This helps me greatly, now I can pick a path forward for hardware.  I appreciate your patience.